Due to the development of electrically erasable and programmable non-volatile storage devices (electrically erasable and programmable read only memory—EEPROM), EEPROMs, such as flash EEPROMs can be used as alternative storage devices, replacements for magnetic storage medium, or the like. Flash EEPROMs are EEPROMs that are arranged in blocks of memory cells that are simultaneously erased.
Referring now to FIG. 10(a), a floor plan of a conventional flash memory chip layout is set forth in a top plan view. In order to utilize the characteristics of non-volatility, the memory is used by repeating erase and write cycles. In order to reduce chip size and for compatibility with a hard disk system or the like, erasing is performed on a unit that includes a plurality of memory cells. The unit of memory cells erased in a block is called a sector.
The conventional flash memory chip 1000 shown in the example of FIG. 10(a) includes 64 sectors (S00–S63), a logic section 11, and a charge pump capacitor 12. Charge pump capacitor 12 serves as a booster circuit and supplies a high electric voltage (Vpp) for writing, for example. Logic section 11 includes an erase and verify circuit for erasing in sector units, a write circuit for controlling writing to a memory cell, a read circuit for controlling reading from a memory cell, and a power supply control circuit, for example.
In an erasing operation, all bits in memory cells (memory cell transistors having floating gates) that are in the same sector are erased simultaneously. The erasing operation requires sufficient time to extract electrons from the floating gates through FN (Fowler-Nordheim) tunneling, for example, plus the time for erase verification or other such steps to provide uniform erasing characteristics. Thus, compared to a reading operation, an erasing operation requires a greater amount of time.
Further, in a case where all sectors (S00–S63) are being used, when one of the sectors (S00 to S63) is erased and then rewritten, the erasing procedure and then the writing procedure will be performed in a sequential order.
FIG. 11 is a table showing an erase/write procedure. In FIG. 11, physical sector numbers (0–63) are shown in the vertical direction and logical sector address and erase/write changes are shown along the horizontal direction. In this example, the physical sector number (also referred to as a “physical sector address”, indicating the address of the sector unit in a physical sector space), and the logical sector number (also referred to as a “logical sector address”, corresponding to a logical address for accessing the sector from a host system), correspond to each other in a one-to-one fashion. In FIG. 11, in the case where the sector at logical sector number 63 (physical sector number 63 in this case) is to be rewritten, the sector at physical sector number 63 is erased and re-writing (indicated as Prog in FIG. 11, i.e. programming) is performed.
Subsequently, the sector at a logical sector number 3 (therefore, physical sector number 3) is erased and rewriting (Prog) is performed.
At erase/write 3 and 5, the sector at physical sector number 63 is erased and rewriting (Prog) is performed again.
At erase/write 6 and 7, the sector at a physical sector 2 is erased and rewriting (Prog) is performed in succession.
The amount of time required per sector for the erase routine is approximately 1 second (preprogram+erase+rewriting). In the case where every bit in the sector is to be written, the writing also requires approximately 0.5 seconds. Therefore, including the erase routine, 1.5 seconds or more are required to rewrite a sector.
Further, the writing and erasing steps of a flash memory usually uses a F-N (Fowler-Nordheim) tunneling or a CHE (channel hot electron) injection method. In a writing step, for example, a high voltage is applied to the control gate and drain of a floating gate type memory cell while the source is grounded. In this way, hot electrons generated in the vicinity of the drain are injected into the floating gate. In the erasing step, for example, F-N tunneling or the like is used to pull electrons from the floating gate to the source, drain, etc. Thus, erasing and writing are performed through a silicon oxide film (gate insulating film or tunnel oxide film) of the floating gate memory cell transistor by adding and removing electrons to and from the floating gate. These steps of writing and erasing the flash memory causes damage to the silicon oxide film. Therefore, the number of times the write/erase rewriting steps can be performed is limited on the order of 100,000 to 1,000,000 times.
In the case where data in the conventional flash memory is to be rewritten, the sector including the memory cells in which data is rewritten is erased. After erasing, the same sector is written with new data.
As shown in FIG. 11, erasing and writing (Prog) is performed in a sequential fashion in order to rewrite data in a sector. Thus, for the data rewriting, an amount of time defined as [erase time for 1 sector]+[writing time] is necessarily required.
In other words, in a conventional flash memory, writing of new data can be performed only after physically erasing data in sector units (corresponding to sector units in which new data is being written). Therefore, the erase time+writing time are needed. The amount of time required for this is much greater than the time required for reading data from a memory cell. As described above, the time required for rewriting is considered to be on the order of 1.5 seconds or longer. As shown in FIG. 11, in the case where the erasing of the physical sector number 2 is repeated consecutively (erase/write 6 and 7), access to the conventional flash memory is forced to wait for a duration of time equivalent to the time required for consecutive rewriting operations, for example.
In a case where the number and frequency of erasing/writing times at one sector gets concentrated than at another sector, the lifetime of the flash memory can be shortened. That is, in the case where a number of erase/write repetition times to the same sector exceeds the limit, the flash memory becomes unusable. When the frequency of rewriting is concentrated more in one sector than in another, the time period that the sector can be used is shortened. Further, as the flash memory is being used for a variety of purposes, the demand to increase the number of write/erase repetition times and achieve a longer lifetime is growing.
Japanese Patent Application Laid Open No. Hei 9-81332 (JPA '332) discloses a conventional flash disk card that can effectively use a flash memory for a longer period of time. Referring now to FIG. 13, a diagram of the configuration of a conventional flash disk card as disclosed in JPA '332 is set forth. Conventional flash disk card includes a flash memory 400 composed of M sectors, or M sectors and r redundant sectors and a logical/physical address conversion table 91. Logical/physical address conversion table 91 outputs a physical sector number 1 through N, or 1 through N and M+1 through M+r, in response to input of a logical sector number 1 through N, which is less than M. Conventional disk card of JPA '332 also includes a means for erasing data at a physical sector number defined by table 91, writing data to be updated into an unused sector or a sector where data is already erased, and changing the physical sector number which the table 91 outputs in response to the logical number L to the number of the sector that the data to be updated was written into when the data in a logical sector number L that is equal to or less than N is to be updated. Conventional disk card of JPA '332 also includes reading means for reading out the physical sector number determined by the table in a case where the inputted logical sector number L is less than N, and reading out the data at a physical sector number L in a case where the number L is greater than N. Each sector has an area into which is written information indicating whether there is a problem or not (problem/normal). A RAM 900 stores and manages a defective sector replacement table 92. When there is a problem in a sector and the physical address and logical address are not converted, the sector is replaced with the redundant sector.
In FIG. 13, a 512-byte sector data area 500 stores the data of the sector (512 bytes), which is the data accessing unit in the hard disk system. A 16-byte sector management data area 501 stores the logical sector number (LSN) of that sector, ECC (error correction codes) data of the data in that sector, and data of flag information indicating the validity of that sector, for example. Memory space of the flash memory 400 is composed of a first area 503, a second area 504, and a third area 505. The first area 503 is an area composed of sectors which are frequently rewritten by a host system (not shown in FIG. 13). The first area 503 is composed of sectors having physical sector numbers 1 through N. The physical sector number to be accessed by the host system is determined based on the logical physical address conversion table 91 stored in the RAM 900. The second area 504 is an area for storing file data. The second area 504 is composed of sectors at the physical sector number N+1 though M. The physical sector number, which the host system accesses, is the same as the logical sector number. The third area 505 is a redundancy area and composed of sectors at physical sector numbers M+1 through M+r. In the case where a defect is generated in the sector having the logical sector number L, the management area of that sector is written with data indicating invalidity, and one of the r redundant sectors is written with data. Also, the redundant sector that the data was written into as logical sector number L is stored in the defective sector replacement table 92. However, in the conventional flash card disk of JPA '332, the address conversion table for converting the logical sector number to the physical sector number is provided in a RAM. As a result, in the case where a power break occurs, the address conversion information in the address conversion table is lost. JPA '332 lacks an awareness of the problem of how to improve sector erase speed.
In view of the above discussion, it would be desirable to provide a non-volatile storage device and a control method for the same in which apparent rewriting time may be significantly reduced in a non-volatile storage device having a flash memory or a flash memory chip. It would also be desirable to provide a non-volatile storage device and a control method for the same in which frequency of usage may be balanced among sectors. It would also be desirable to provide a non-volatile storage device which may have an increased lifetime.